Many devices, particularly handheld devices, are required to operate for long periods of time on battery power. To operate in this manner, such devices often support one or more lower power modes of operation, such as while waiting to receive a message or phone call. During such times, various parts of these devices may be put into a low power mode that reduces their power consumption. This is sometimes also called sleep mode.
One way to achieve the lowest sleep power is to shut down the power domain blocks which are not needed in a low power mode or sleep mode. For example, in a WiFi device, the Baseband and MAC blocks contribute up to 40-50% of the total digital leakage power. However, to be able to shut down Baseband and MAC, all the dynamic logic states and software configurations are required to be maintained. In another words, hardware states and configurations need to be saved before going to sleep and restored after completing the sleep mode. Two common methods to achieve this process are the usage of state-retention flip-flops or the usage of a complete software management of the operation. State-retention flip-flops are expensive to implement. It requires the implementation of dual power rails and increase in gate size. Alternatively, a complete software management of the operation is time consuming and requires considerable power consumption.
To develop an improved low power mode solution for digital systems, one needs to understand the properties of logic circuits. Logic circuits are frequently composed of logic cells that may store bits and/or operate on bits. The logic cells are often part of a library of cells that have been designed, not only electrically but also as layout templates, simulated, verified and tested for the specific semiconductor manufacturing process for the intended integrated circuit.
Examples of logic cells often found in cell libraries include, but are not limited to, logic gates and latches. Examples of logic gates include nand and nor gates. Logic latches tend to maintain an internal state that forms their output. Examples of latches include D flip-flops and R-S latches. Latches may not be able to maintain their internal state during low power mode, leading to the possibility of the internal state being corrupted. Logic gates during low power mode tend to continue to dissipate power in the form of leakage current. The amount of leakage current dissipated may vary for a logic gate for different inputs in low power mode.
Another set of logic circuits are known as Finite State Machines (FSM), which are typically configured to receive at least one input, maintain and update at least one state and generate at least one output based upon the value of at least one of the inputs and/or the value of at least one of the states. FSM may include instances of logic gates and/or latches. A processor comprises finite state machines. Hence, an integrated circuit with processor or computational elements also comprises finite state machines.
Many integrated circuits include FSM, which have internal states that are neither read nor written by any bus. Today, retaining the states of these FSM through low power mode often requires the use of state-retention flip-flops, which are expensive to implement and manufacture through their use of dual power rails and the increased size of these flip-flops.
Many integrated circuits require tables of dynamic state/configuration information to be retained through low power mode. Today such tables can only be retained through the use of a software based retention and restoration process that takes a comparatively long time, and as a consequence, consumes a lot of power.
What is needed is an apparatus for these integrated circuits that can retain and restore the states of FSM and/or tables of dynamic state/configuration information that is faster and more energy efficient than the software approach but without using the state-retention flip-flops.